Differences

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--- jdm:pc9801:ports [2021/12/25 12:19] – created asie
+++ jdm:pc9801:ports [2022/02/18 22:36] (current) – asie
@@ Line 24: / Line 24: @@
 TODO
+===== 7Ch (GRCG - Control) =====
+  * bit 7 - enable (1)/disable (0) GRCG
+  * bit 6 - enable (1)/disable (0) read/modify/write mode
+  * bit 4-5 - select plane exposed to CPU (0-3)
+  * bit 3 - enable (1)/disable (0) plane 3
+  * bit 2 - enable (1)/disable (0) plane 2
+  * bit 1 - enable (1)/disable (0) plane 1
+  * bit 0 - enable (1)/disable (0) plane 0
+===== 7Eh (GRCG - Tile) =====
+This port accepts sequential (in order of enabled planes) 8-bit tile data.